As integrated circuits (ICs) become more complicated and, as a result, denser, the metal-oxide-semiconductor (MOS) circuit elements that make up the IC must become smaller. As the size of a MOS circuit element shrinks, its operating voltage also tends to drop. In the past, the standard operating voltage of MOS circuit elements was 5V. Newer designs are using operating voltages in the 2.5 to 3.3 volt range. For compatibility, it is desirable for the newer designs to be able to withstand 5V signals. Unfortunately, technologies developed for 3V operation have thin gate oxides (on the order of 100 .ANG.). If a thin oxide device designed for 3V operation were instead operated at 5V, the device would have accelerated wear-out due to reduced gate oxide reliability.
ESD protection circuits are typically designed with thin gate oxide devices to improve switching speed and current homogeneity. Hence, ESD protection circuits using MOS circuit elements must be designed to avoid having the oxides stressed by a 5V bond pad voltage during normal operation. At the same time, the protection circuit must turn-on and provide good ESD protection during ESD stress.
One prior art solution uses two gate oxide thicknesses. A thinner oxide is used for the internal circuitry and a thicker oxide is used for circuitry connected directly to a bond pad. Unfortunately, this adds process complexity by requiring two gate oxide formations. Thus, there is a need for ESD protection circuitry that will not be stressed during 5V operation and that minimizes process complexity.